1. Field of the Invention
This invention relates generally to high performance transistor devices and, more particularly, to low threshold voltage transistors. Specifically, the present invention relates to low Vt semiconductor devices having improved implanted well structure which permits short channel design while substantially reducing punch through characteristics, reduced threshold variation and high mobility.
2. Discussion of the Related Art
As the semiconductor industry has advanced, the sizes of active semiconductor transistor devices have shrunk to sub-micron dimensions. This has required the formation of devices that push the limits of known manufacturing techniques and processes. Semiconductor devices formed with a short channel length are particularly affected by manufacturing process variations. For example, short channel MOS (Metal Oxide Semiconductor) transistor devices can be difficult to manufacture with acceptable threshold voltage (Vt) control.
In a MOS transistor, the threshold voltage is the voltage or potential that must be applied to the gate region of the transistor before a current will flow in the channel below to the gate region between the source and drain. In general, higher threshold voltages are undesirable because higher power supplies are required for operating the semiconductor devices. In addition, with higher threshold voltages, the semiconductor devices are slower. As power supply voltage decreases, analog circuitry can be adversely affected as the devices are stacked between Vdd and Vss. Moreover, this loss of xe2x80x9cheadroomxe2x80x9d reduces the available voltage swing. Moreover, if the threshold voltage of an access device for a memory cell is too high, then it is more difficult to write data into the cell.
As MOS technology has evolved, the supply voltage (Vdd) has also scaled with the size of the devices. For example, as channel lengths have decreased, the supply voltages have correspondingly decreased. In many applications, it is desirable to provide lower supply voltages for given device sizes. This is because devices requiring lower supply voltages generally conserve power, a feature which is particularly desirable in systems which dissipate large amounts of energy or rely on limited power sources such as batteries. However, there has been some concern about the effects of low supply voltage on device performance.
In circuits made up of conventional MOS devices, the relationship of maximum frequency, or the performance of the circuit, to supply voltage and threshold voltage is governed by the long and short channel effects of the component MOS devices. It has been found that the performance of a circuit made up of truly long channel devices is dependent on the absolute value of the supply voltage. Consequently, if the supply voltage to the devices in such circuits is lowered, then performance is also lowered. However, in circuits made up of truly short channel devices, performance is governed by the ratio of threshold voltage to supply voltage. This means that in such circuits, the supply voltage can be lowered with no loss in performance so long as the threshold voltage is also lowered to maintain a constant Vt/Vdd ratio.
Thus, while low threshold voltage MOS devices appear to be desirable, there have been certain problems associated with such devices in the past. First, as the threshold voltage is lowered, the drain-to-source leakage current of the transistor increases. Leakage current is that current which flows across the channel region when the transistor is turned off. In applications where the device must frequently switch, such as in microprocessors, this does not cause a problem. However, in other applications where the device is normally inoperative or inactive, such as in memory devices, this is a significant problem. Moreover, in short channel devices having a low threshold voltage, the distance between the drain and source regions is very small, and if this distance becomes too small, the depletion regions of the source and drain in the channel region can overlap to cause punch through. When this occurs, current flows through the path between the source and drain created by the depletion regions overlapping even when the transistor is turned off. In such instances, the gate control of the channel is lost.
There have been numerous attempts to develop transistor devices which overcome the aforementioned problems. Some examples of these efforts are illustrated in U.S. Pat. Nos. 5,493,251, 5,529,940, 5,589,701, 5,661,045, 5,622,880 and 5,719,422. It is known that the threshold voltage of a short channel MOS device is very sensitive to the dopant concentration of the substrate of the device. As a result, many approaches used to form low threshold devices rely on counter-doping the xe2x80x9cstandardxe2x80x9d threshold devices, resulting in significant mobility degradation. Conversely, approaches that rely on xe2x80x9cnaturalxe2x80x9d or very low doping levels suffer from short channel Vt rolloff or punch through. It is also known that the variation of the threshold voltage is affected by the number of implant steps required to set the Vt. Hence, counter-doped devices have higher variability. Moreover, in both high and low threshold voltage devices, it is known that a buried electrode region of relatively high dopant concentration will help to suppress growth of depletion regions and thereby reduce punch through. However, there is still a need for an improved high performance, short channel transistor device having a low threshold voltage which experiences little if any punch through characteristics while maintaining high mobility and low threshold variation.
Accordingly, it is one object of the present invention to provide an improved semiconductor device.
It is another object of the present invention to provide a low threshold voltage semiconductor device which exhibits reduced punch through.
Yet another object of the present invention is to provide a low threshold voltage semiconductor device having a buried electrode region below the source and drain regions of the device which permits short channel design with reduced punch through characteristics, reduced threshold variation and high mobility.
Still another object of the present invention is to provide a method of manufacturing such a semiconductor device.
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, as embodied and broadly described herein, a low threshold voltage MOS device on a semiconductor substrate is disclosed along with its method of manufacture. The substrate has an upper surface, and a first well region is disposed in the semiconductor substrate extending downwardly from the semiconductor substrate upper surface. The first well region includes a dopant of a first conductivity type having a first average dopant concentration. Source and drain regions of a second conductivity type are laterally spaced from each other and are disposed in the first well region, the source and drain regions extending downwardly from the semiconductor substrate upper surface a predetermined distance.
A channel region made up of the first well region of the first conductivity type is disposed between the source and drain regions. The channel region also extends at least the predetermined distance below the semiconductor substrate upper surface. A second well region is disposed in the semiconductor substrate below the channel region, the second well region being of the first conductivity type having a second average dopant concentration. A buried electrode region is disposed below the source and drain regions between the second well region and the channel region. The buried electrode region has a dopant of the first conductivity type at a relatively low concentration which is nonetheless greater than both the first and second dopant concentrations of the channel region and the second well region, respectively. Finally, a gate is disposed over the channel region with the buried electrode creating a low gate threshold voltage with significantly reduced likelihood of punch through.